1. Field of the Invention
The present invention relates generally to a charged beam exposure system using electron beams etc for writing a pattern of a semiconductor integrated circuit such as an LSI etc on a sample such as a wafer and a mask at a high speed with a high accuracy, and more particularly to a charged beam pattern writing system contrived to enhance a throughput of the pattern writing by optimizing a stage speed.
2. Description of the Background Art
With scaling-up of a semiconductor device and as well fining of elements included therein, there widely spreads a pattern writing technology of writing a pattern on a wafer or mask by use of a charged beam exposure system.
In such a charged beam pattern writing technology, a range in which the charged beams can be deflected is limited, and the pattern is written by making the beams consecutively scan in an orthogonal direction (an X-direction) the reticle or the mask defined as a sample placed on the stage while deflecting the beams within a main deflection width (a Y-direction). Therefore, as shown in FIG. 33, for instance, a unit pattern writing area corresponding to a chip area is partitioned into frame fields F1-FN each defined by the main deflection beam deflection width. In FIG. 33, points P1-PN respectively denote frame originating points of the frame fields F1-FN. This type of pattern writing method is referred to as normal writing.
On the other hand, there has been carried out a pattern writing method of writing the same pattern a plurality of times while controlling a beam irradiation quantity of the charged beams for the purpose of enhancing a pattern dimensional accuracy, which is called a multi pattern writing. In the multi pattern writing, the pattern writing of a stripe field corresponding to a frame in the normal pattern writing, and a step movement is made in the direction (Y-direction) orthogonal to the stage moving direction. The above processes are repeated, thereby writing the pattern in all the stripe fields. This step movement corresponds to a width that is 1/number-of-multi-writings of a frame width.
FIG. 34 shows a concept of the multi-writings described above, wherein double writings are shown in this example, and the stripe field is shifted by half a width of the frame field. In this figure, Ps1-Psm denote stripe originating points of stripe field S1-SM and a main-deflection beam deflection width equals to a stripe field width. The main-deflection beam deflection width equals to the stripe field width.
Further, the frame or stripe field is, if the necessity may arise, subdivided into sub-deflection fields in which the beams can be deflected by a sub-deflection beam deflector.
In the charged beam pattern writing method explained above, a pattern writing speed is constant in the frame or stripe field. Further, a patten writing time (for writing a desired pattern by controlling a beam position and a beam configuration) defined in the frame or stripe field must be a value enough to follow up the stage speed when writing the pattern in the frame or stripe field.
The following methods have hither been proposed for determining the stage speed which might satisfy the above condition.
(i) A stage speed for executing a process of writing the pattern in the frame field, is determined based on a total number of shots embraced in the frame field and a total number of sub-deflection fields (refer to Japanese Patent Application Laid-Open Publication No.1-152726).
(ii) A stage speed for executing a process of writing the pattern in the frame field is determined based on a virtual number of shots which is obtained by dividing a total areal size of the pattern embraced in the frame field by an average areal size of one shot, and on a total number of sub-deflection fields (refer to Japanese Patent Application Laid-Open Publication No.1-243520).
(iii) The frame field is virtually partitioned into segments each having a predetermined length, a number of shots is calculated per partitioned segment, a pattern writing time in the segment having a maximum number of shots, and a value obtained by dividing this pattern writing time by the length of the segment is set as a stage speed for executing the process of writing the pattern in the frame field (refer to Japanese Patent Application Laid-Open Publication No.2-5406).
There arise, however, the problems inherent in the conventional speed determining methods.
According to the conventional methods (i), (ii), the average stage speed is determined based on such a premise that the patterns are uniformly disposed in the frame field. In an actual LSI device pattern, however, a pattern layout in the frame field is not uniform, and a pattern density is not uniform, wherein a high pattern density area and a low pattern density area alternately exist. Generally, a longer pattern writing time is needed for writing the pattern in the high pattern density area.
Hence, at the speeds calculated by the conventional methods (i) and (ii), a writing error (caused when the pattern writing process is unable to follow up the stage speed) does not occur in the pattern writing in the low pattern density area, but occurs in the high pattern density area. The problem is that the stage speed is decreased, and the pattern writing process in the concerned frame field must be again carried out.
On the other hand, according to the method (iii), the frame field is virtually partitioned into block segments, and the speed is determined for the block segment, thus considering the problem derived from the low pattern density, which remains unsolved by the conventional methods (i) and (ii). Resultantly, however, the method (iii) is no better than obtaining the average speed in the block regions.
For example, as shown in FIG. 36, the frame is partitioned into five blocks each having a width W, thus virtually defining the blocks. Assuming an example in which a high pattern density region A extend to some parts of both of the blocks 3, 4, according to the method (iii), it follows that the pattern is written in the block at the stage speed (V3=W/T) determined in the block 3.
However, though this speed V3 is optimal to only the block 3 in terms of the pattern writing, actually the pattern writing is effected consecutively in the block 3 and the block 4. Therefore, a stage speed optimal the pattern writing in the region A extending to both of the blocks 3, 4 is given by V34=W/2T. Accordingly, there might be a possibility in which the error occurs in the pattern writing because of the pattern writing process being unable to follow up the stage movement in terms of the relationship of V3 greater than V34. Hence, the problem is that the stage speed is decreased as in the case of the methods (i), (ii), and the pattern writing process must be re-executed.
Moreover, the stage speed in the stripe field in the multi pattern writings, on the occasion of determining it, can be calculated by the conventional methods (i), (ii), (iii). However, for instance, as shown in FIG. 37, a chip composed of five frame fields F1-F5 undergoes the multi pattern writings of which the number is 4, with the result that the number of stripe fields is 23 given in the following formula.
Number-of-stripe-fields=number-of-frame-fields+(number-of-multi-pattern-writingsxe2x88x921)xc3x97(frame field+1)
Therefore, in this case, the process is executed for all the stripe fields (23 fields), wherein the number of writings is over N-times as large as the normal writings.
As described above, when writing the pattern at the stage speed obtained by the conventional methods, there might be a possibility in which the error occurs in the pattern writing. Further, a stage speed calculation processing time that is over N-times as large as the time in the normal writing, is needed in the multi pattern writing effected N times. This leads to an increase in the pattern writing time, i.e., a decline of throughput of the whole exposure system.
Accordingly, it is a primary object of the present invention to provide a charged beam exposure system which is capable of determining a stage speed per frame field or stripe field a stage speed optimal enough to cause no error in pattern writing in consideration of a degree of pattern density in the frame field in normal pattern writing or in the stripe field in multi pattern writings, and also enhancing a throughput.
It is another object of the present invention to provide a charged beam exposure system which is capable of determining writing speed per stripe in the multi pattern writings optimal enough to cause no error in the pattern writing, and also calculating the stage speed at a high speed.
According to the present invention, each of blocks constituting a frame is partitioned into fixedly or arbitrarily determined segments, and a block pattern writing speed is determined based on a pattern writing time in this segment or a moving speed therein, and it is therefore feasible to enhance the throughput of the charged beam pattern writing apparatus by determining stage speed per frame field or stripe field which is optimal enough to cause no error in the pattern writing in consideration of the degree of pattern density in the frame field or the stripe field, and for the multi pattern writings, by high speed calculating the stage speed in a stripe field.